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cy7c603xx encore? iii low voltage cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-16018 rev. *g revised january 15, 2010 features powerful harvard architecture processor ? m8c processor speeds to 12 mhz ? low power at high speed ? 2.4v to 3.6v operating voltage ? operating voltages down to 1.0v using on-chip switch mode pump (smp) ? commercial temperature range: 0c to +70c configurable peripherals ? 8-bit timers, counters, and pwm ? full duplex master or slave spi ? 10-bit adc ? 8-bit successive approximation adc ? comparator flexible on-chip memory ? 8k flash program storage 50,000 erase/write cycles ? 512 bytes sram data storage ? in-system serial programming (issp) ? partial flash updates ? flexible protection modes ? eeprom emulation in flash complete development tools ? free development software (psoc designer?) ? full-featured, in-circuit emulator and programmer ? complex breakpoint structure ? 128k trace memory precision, programmable clocking ? internal 2.5% 24 and 48 mhz oscillator ? internal oscillator for watchdog and sleep programmable pin configurations ? 10 ma drive on all gpio ? pull up, pull down, high z, strong, or open drain drive modes on all gpio ? up to 8 analog inputs on gpio ? configurable interrupt on all gpio versatile analog mux ? common internal analog bus ? simultaneous connection of io combinations additional system resources ? i 2 c master, slave and multi-master to 400 khz ? watchdog and sleep timers ? user-configurable low voltage detection ? integrated supervisory circuit ? on-chip precision voltage reference applications wireless mice wireless gamepads wireless presenter tools wireless keypads playstation ? 2 wired gamepads playstation 2 bridges for wireless gamepads ? applications requiring a cost effective low voltage 8-bit microcontroller. digital system sram 512 bytes system bus interrupt controller clock sources (includes imo and ilo) global digital interconnect global analog interconnect cpu core (m8c) srom flash 8k system resources analog system analog ref. digital clocks i2c por and lvd system resets internal voltage ref. switch mode pump port 1 port 0 sleep and watchdog analog mux port 3 port 2 analog psoc block array digital psoc block array encore ii lv core block diagram [+] feedback
cy7c603xx document number: 38-16018 rev. *g page 2 of 34 contents features ............................................................................. 1 applications ...................................................................... 1 block diagram .................................................................. 1 contents ............................................................................ 2 encore iii low voltage functional overview ................ 3 encore iii lv core ..................................................... 3 the digital system ...................................................... 3 the analog system ..................................................... 3 additional system resources ..................................... 4 encore iii lv device characteristics ............................. 4 getting started .................................................................. 4 development kits ........................................................ 4 development tools .......................................................... 5 psoc designer software subsyst ems .......... .............. 5 hardware tools ........................................................... 5 designing with user modules ......................................... 6 document conventions ................................................... 7 units of measure ......................................................... 7 numeric naming .......................................................... 7 pin information ................................................................. 8 28-pin part pinout ... .............. .............. .............. .......... 8 32-pin part pinout ... .............. .............. .............. .......... 9 register reference ......................................................... 11 register conventions ................................................ 11 register mapping tables ...... .............. .............. ........ 11 electrical specifications ................................................ 15 absolute maximum ratings ... .................................... 16 operating temperature ............................................. 16 dc electrical characteristics ..................................... 16 ac electrical characteristics ..................................... 22 packaging information ................................................... 29 packaging dimensions .............................................. 29 thermal impedances ................................................ 31 solder reflow peak temperat ure ............................. 31 package handling ........................................................... 31 ordering information ...................................................... 32 document history page ................................................. 33 sales, solutions, and legal information ...................... 34 worldwide sales and design s upport ......... .............. 34 products .................................................................... 34 psoc? solutions ...................................................... 34 [+] feedback
cy7c603xx document number: 38-16018 rev. *g page 3 of 34 encore iii low voltage functional overview the encore iii low voltage (encore iii lv) cy7c603xx device is based on the flexible psoc ? architecture. this supports a simple set of peripherals that can be configured to match the needs of each application. additionally, a fast cpu, flash program memory, sram data memo ry, and configurable io are included in a range of convenient pinouts. this architecture enables the user to create customized peripheral configurations that match the requirements of each individual application. a fast cpu, flash program memory, sram data memory, and configurable io are included in both 28-pin ssop and 32-pin qfn packages. the encore iii lv architecture, as shown in figure 1 , consists of four main areas: the encore iii lv core, the system resources, digital system, and analog system. configurable global bus resources allow combining all the device resources into a complete custom system . each encore iii lv device supports a limited set of digital and analog peripherals. depending on the package, up to 28 general purpose ios (gpios) are also included. the gpios provide access to the global digital and analog interconnects. encore iii lv core the encore iii lv core is a powerful engine that supports a rich feature set. it encompasses sram for data storage, an interrupt controller, sleep and watchdog timers, and imo (internal main oscillator) and ilo (internal low-speed oscillator). the cpu core, called the m8c, is a powerful processor with speeds up to 12 mhz. the m8c is a four mips 8-bit harvard architecture microprocessor. the core includes a cpu, memory, clocks, and configurable gpio (general purpose io). system resources provide additional capability, such as digital clocks to increase flexibility, i2c functionality for implementing an i2c master, slave, multi-master, an internal voltage reference that provides an absolute va lue of 1.3v to a number of subsystems, a switch mode pump (smp) that generates normal operating voltages off a single battery cell, a nd various system resets supported by the m8c. the digital system the digital system consists of 4 digital encore iii lv blocks. each block is an 8-bit resource. digital peripheral configurations include the following: pwm usable as timer or counter spi master and slave i2c slave and multi-master cmp adc10 saradc figure 1. digital system block diagram the digital blocks may be connected to any gpio through a series of global buses that can route any signal to any pin. the buses also allow for signal multiplexing and for performing logic operations. this configurability frees your designs from the constraints of a fixed peripheral controller. the analog system the analog system consists of two configurable blocks. analog peripherals are very flexible and may be customized to support specific application requiremen ts. some of the common analog functions for this device (available as user modules) are: analog-to-digital converters (single with 8-bit resolution) pin-to-pin comparators single-ended comparators with absolute (1.3v) reference 1.3v reference (as a system resource) analog blocks are provided in columns of two, which includes one ct (continuous time - ace00 or ace01) and one sc (switched capacitor - ase10 or ase11) blocks. digital system to system bus d i g i t a l c l o c k s f r o m c o r e digital encore ii lv block array to analog system 8 row input configuration row output configuration 8 8 8 row 0 dbb00 dbb01 dcb02 dcb03 4 4 gie[7:0] gio[7:0] goe[7:0] goo[7:0] global digital interconnect port 3 port 2 port 1 port 0 [+] feedback
cy7c603xx document number: 38-16018 rev. *g page 4 of 34 figure 2. analog system block diagram the analog multiplexer system the analog mux bus can connect to every gpio pin. pins are connected to the bus individually or in any combination. the bus also connects to the analo g system for analysis with comparators and analog-to-digital converters. an additional 8:1 analog input multiplexer provides a second path to bring port 0 pins to the analog array. additional system resources system resources, some of wh ich are listed in the previous sections, provide additional capability useful to complete systems. additional resources include a switch mode pump, low voltage detection, and power on reset. brief statements describing the merits of each system resource follow. digital clock dividers provide three customizable clock frequencies for use in applications. the clocks can be routed to both the digital and analog systems. additional clocks may be generated using di gital blocks as clock dividers. the i 2 c module provides 100 khz and 400 khz communication over two wires. slave, master, and multi-master modes are all supported. low voltage detection (lvd) interrupts can signal the application of falling voltage levels, while the advanced por (power on reset) circuit eliminates the need for a system supervisor. an internal 1.3 voltage reference provides an absolute reference for the analog system. an integrated switch mode pump (smp) generates normal operating voltages from a single 1.2v battery cell, providing a low-cost boost converter. versatile analog mu ltiplexer system. encore iii lv device characteristics the encore iii lv devices have four digital blocks and four analog blocks. table 1 lists the resources available for specific encore iii lv devices. getting started the quickest path to understanding the encore iii lv silicon is by reading this data sheet and using the psoc designer integrated development environment (ide). this data sheet is an overview of the encore iii lv and presents specific pin, register, and electrical specifications. encore iii lv is based on the architecture of the cy8c21x34. for in-depth information, along with detailed programming information, refer to the psoc programmable system-on-chip technical reference manual , which is available at http://www.cypress.com/psoc . for up-to-date ordering, packaging, and electrical specification information, refer to the latest device data sheets on the web at http://www.cypre ss.com/go/usb . development kits development kits are available from the following distributors: digi-key, avnet, arrow, and future. the cypress online store contains development kits, c compilers, and all accessories for encore iii lv development. go to the cypress online store web site at http://www.cypress.com , click the online store shopping cart icon at the bottom of the web page, and click usb (universal serial bus) to view a current list of available items. acol1mux ace00 ace01 array array input configuration ase10 ase11 x x x x x analog mux bus all io aci0[1:0] aci1[1:0] table 1. encore iii lv device characteristics part number digital io digital rows digital blocks analog inputs analog outputs analog columns analog blocks sram size flash size cy7c60323- pvxc 24 1 4 24 0 2 4 512 bytes 8k cy7c60323- lfxc 28 1 4 28 0 2 4 512 bytes 8k cy7c60333- lfxc 28 1 4 26 0 2 4 512 bytes 8k [+] feedback
cy7c603xx document number: 38-16018 rev. *g page 5 of 34 development tools psoc designer is a microsoft ? windows ? based, integrated development environment for the encore iii lv. the psoc designer ide and application runs on windows xp and vista. (see figure 3 ) psoc designer helps the customer to select an operating configuration, write application code that uses the encore iii lv, and debug the applic ation. this system provides design database management by projec t, an integrated debugger with in-circuit emulator, in-system programming support, and the cyasm macro assembler for the cpus. psoc designer also supports a high level c language compiler developed specifically for the devices in the family. figure 3. psoc designer subsystems psoc designer software subsystems device editor the device editor subsystem enables the user to select different on-board analog and digital components called user modules using the blocks. examples of user modules are adcs, pwms, and spi. psoc designer sets up power on initialization tables for selected block configurations and creates source code for an application framework. the framework contains software to operate the selected components and, if the project uses more than one operating configuration, contains routines to switch between different sets of block configurations at run time. psoc designer can print out a configuration sheet for a given project configuration for use during application programming in conjunction with the device data sheet. after the framework is generated, the user can add application-specific code to flesh out the framework. it is also possible to change the selected components and regenerate the framework. application editor in the application editor, you can edit your c language and assembly language source code. you can also assemble, compile, link, and build. assembler. the macro assembler allows the assembly code to be merged seamlessly with c code. the link libraries automatically use absolute addressing or can be compiled in relative mode and linked with other software modules to get absolute addressing. c language compiler. a c language compiler that supports the encore iii lv family of devices is available. even if you have never worked in the c language before, the product quickly allows you to create complete c programs. the embedded, optimizing c compiler provides all the features of c tailored to the encore iii lv architecture. it comes complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. debugger the psoc designer debugger subsystem provides hardware in-circuit emulation, enabling des igners to test the program in a physical system while providing an internal view of the device. debugger commands allow the designer to read the program and read and write data memory, read and write io registers, read and write cpu registers, set and clear breakpoints, and provide program run, halt, and st ep control. the debugger also allows the designer to create a trace buffer of registers and memory locations of interest. online help system the online help system displays on line, context-sensitive help for the user. designed for procedural and quick reference, each functional subsystem has its ow n context-sensitive help. this system also provides tutorials an d links to faqs and an online support forum to aid the designer in getting started. hardware tools in-circuit emulator a low cost, high functionality ice (in-circuit emulator) is available for development support. this hardware has the capability to progra m single devices. the emulator consists of a base unit that connects to the pc by way of a usb port. the base unit is universal and operates with encore iii lv, encore iii, and all psoc devices. emulation pods for each device family are available separately. the emulation pod takes the place of the encore iii lv device in the target board and performs full speed (12 mhz) operation. commands results psoc designer core engine psoc configuration sheet manufacturing information file device database importable design database device programmer graphical designer interface context sensitive help emulation pod in-circuit emulator project database application database user modules library psoc designer [+] feedback
cy7c603xx document number: 38-16018 rev. *g page 6 of 34 designing with user modules the development process for the encore iii lv device differs from that of a traditional fixe d-function microprocessor. the configurable analog and digi tal hardware blocks provide a unique flexibility that pays divi dends in managing specification change during development and by lowering inventory costs. these configurable resources have the ability to implement a wide variety of user-selectable functions. each block has several registers that determine its fu nction and connectivity to other blocks, multiplexers , buses and to the io pins. iterative development cycles permit you to adapt the hardware and software. this substantially lowers the risk of having to select a different part to meet the final design requirements. to speed the development process, the psoc designer integrated development environm ent (ide) provides a library of prebuilt, pretested hardware peripheral functions, called ?user modules.? user modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. the standard user module library contains seven common periphera ls such as adcs, spi, i2c, and pwms to configure the encore iii lv peripherals. each user module establishes t he basic register settings that implement the selected function. it also provides parameters that allow you to tailor its precise configuration to your particular application. for example, a pulse width modulator user module configures a digital encore iii lv block for 8 bits of resolution. the user module parameters permit you to establish the pulse width and duty cycle. user modules also provide tested software to cut your development time. the user module application programming interface (api) provides high level functions to control and respond to hardware events at run time. the api also provides optional interrupt service routines that you can adapt as needed. the api functions are document ed in user module data sheets that are viewed directly in the psoc designer ide. these data sheets explain the internal operation of the user module and provide performance specificatio ns. each data sheet describes the use of each user module parameter and documents the setting of each register controlled by the user module. the development process starts when you open a new project and bring up the device editor, a graphical user interface (gui) for configuring the hardware. you pick the user modules you need for your project and map them onto the encore iii lv blocks with point-and-click simpli city. next, you build signal chains by interconnecting user modules to each other and the io pins. at this stage, you also configure the clock source connections and enter parameter values directly or by selecting values from drop-down menus. when you are ready to test the hardware configuration or move on to developing code for the project, perform the ?generate application? step. this causes psoc designer to generate source code that automatically configures the device to your s pecification and provides the high level user module api functions. figure 4. user module and source code development flows the next step is to write your main program, and any subroutines using psoc designer?s applic ation editor subsystem. the application editor includes a proj ect manager that allows you to open the project source code files (including all generated code files) from a hierarchal view. the source code editor provides syntax coloring and advanced edit features for both c and assembly language. file search capabilities include simple string searches and recursive ?grep-style? patterns. a single mouse click invokes the build manager. it employs a professional-strength ?ma kefile? system to au tomatically analyze all file dependencies and run the compiler and assembler as necessary. project-level options control optimizat ion strategies used by the compiler and linker. syntax errors are displayed in a console window. double clicking the error message takes you directly to the offending line of source code. when all is correct, the linker builds a hex file image suitable for programming. the last step in the development process takes place inside the psoc designer?s debugger subsystem. the debugger downloads the hex image to the in -circuit emulator (ice) where it runs at full speed. debugger ca pabilities rival those of systems costing many times more. in addition to traditional single-step, run-to-breakpoint and watch-variable features, the debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. debugger interface to ice application editor device editor project manager source code editor storage inspector user module selection placement and parameter -ization generate application build all event & breakpoint manager build manager source code generator [+] feedback
cy7c603xx document number: 38-16018 rev. *g page 7 of 34 document conventions units of measure a units of measure table is locat ed in the electrical specifications section. table 8 on page 15 lists all the abbreviations used to measure the encore iii lv devices. numeric naming hexadecimal numbers are represented with all letters in uppercase with an appended lowercas e ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers may also be represented by a ?0x? prefix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, 01010100b? or ?01000011b?). numbers not indicat ed by an ?h? or ?b? are decimal. table 2. acronyms used acronym description ac alternating current adc analog-to-digital converter api application programming interface cpu central processing unit ct continuous time eco external crystal oscillator eeprom electrically erasable programmable read-only memory fsr full scale range gpio general purpose io gui graphical user interface hbm human body model ice in-circuit emulator ilo internal low speed oscillator imo internal main oscillator io input/output ipor imprecise power on reset lsb least-significant bit lvd low voltage detect msb most-significant bit pc program counter pll phase-locked loop por power on reset ppor precision power on reset psoc? programmable system-on-chip? pwm pulse width modulator sc switched capacitor sram static random access memory [+] feedback
cy7c603xx document number: 38-16018 rev. *g page 8 of 34 pin information the encore iii lv device is available in 28-pin ssop and 32-pin qfn packages. every port pin (labeled with a ?p?) is capable of digital io and connection to the common analog bus. however, vss, vdd, smp, and xres are not capable of digital io. 28-pin part pinout figure 5. cy7c60323-pvxc 28-pin device a, i, m, p0[7] a, i, m, p0[5] a, i, m, p0[3] a, i, m, p0[1] m, p2[7] m, p2[5] m, p2[3] m, p2[1] vss m, i2c scl, p1[7] m, i2c sda, p1[5] m, p1[3] m, i2c scl, p1[1] vss vdd p0[6], a, i, m p0[4], a, i, m p0[2], a, i, m p0[0], a, i, m p2[6], m p2[4], m p2[2], m p2[0], m xres p1[6], m p1[4], extclk, m p1[2], m p1[0], i2c sda, m ssop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 table 3. pin definitions - cy7c60323-pvxc 28-pin device pin no. type name description digital analog 1 io i, m p0[7] analog column mux input. 2 io i, m p0[5] analog column mux input and column output. 3 io i, m p0[3] analog column mux input and column output, integrating input. 4 io i, m p0[1] analog column mux in put, integrating input. 5 io m p2[7] 6 io m p2[5] 7 io i, m p2[3] direct switched capacitor block input. 8 io i, m p2[1] direct switched capacitor block input. 9 power vss ground connection. 10 io m p1[7] i2c serial clock (scl). 11 io m p1[5] i2c serial data (sda). 12 io m p1[3] 13 io m p1[1] i2c serial clock (scl), issp-sclk. 14 power vss ground connection. 15 io m p1[0] i2c serial data (sda), issp-sdata. 16 io m p1[2] 17 io m p1[4] optional external clock input (extclk). 18 io m p1[6] 19 input xres active high external reset with internal pull down. 20 io i, m p2[0] direct switched capacitor block input. 21 io i, m p2[2] direct switched capacitor block input. 22 io m p2[4] 23 io m p2[6] 24 io i, m p0[0] analog column mux input. 25 io i, m p0[2] analog column mux input. 26 io i, m p0[4] analog column mux input. 27 io i, m p0[6] analog column mux input. 28 power vdd supply voltage. legend a: analog, i: input, o = output, and m = analog mux input. [+] feedback
cy7c603xx document number: 38-16018 rev. *g page 9 of 34 32-pin part pinout a, i, m, p0[1] m, p2[7] m, p2[5] m, p2[3] m, p2[1] smp qfn 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 vss p0[3], a, i, m p0[7], a, i, m vdd p0[6], a, i, m p0[4], a, i, m p0[2], a, i, m vss m, 12c scl, p1[7] p0[0], a, i, m p2[6], m p3[0], m xres m, 12c sda, p1[5] m, p1[3] m, 12c scl, p1[1] vss m, 12c sda, p1[0] m, p1[2] m, extclk, p1[4] m, p1[6] p2[4], m p2[2], m p2[0], m p3[2], m p0[5], a, i, m a, i, m, p0[1] m, p2[7] m, p2[5] m, p2[3] m, p2[1] m, p3[3] qfn (top view) 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 vss p0[3], a, i, m p0[7], a, i, m vdd p0[6], a, i, m p0[4], a, i, m p0[2], a, i, m m, p3[1] m, i2c scl, p1[7] p0[0], a, i, m p2[6], m p3[0], m xres m, i2c sda, p1[5] m, p1[3] m, i2c scl, p1[1] vss m, i2c sda, p1[0] m, p1[2] m, extclk, p1[4] m, p1[6] p2[4], m p2[2], m p2[0], m p3[2], m p0[5], a, i, m a, i, m, p0[1] m, p2[7] m, p2[5] m, p2[3] m, p2[1] smp qfn (top view) 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 vss p0[3], a, i, m p0[7], a, i, m vdd p0[6], a, i, m p0[4], a, i, m p0[2], a, i, m vss m, i2c scl, p1[7] p0[0], a, i, m p2[6], m p3[0], m xres m, i2c sda, p1[5] m, p1[3] m, i2c scl, p1[1] vss m, i2c sda, p1[0] m, p1[2] m, extclk, p1[4] m, p1[6] p2[4], m p2[2], m p2[0], m p3[2], m p0[5], a, i, m a, i, m, p0[1] m, p2[7] m, p2[5] m, p2[3] m, p2[1] m, p3[3] qfn 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 vss p0[3], a, i, m p0[7], a, i, m vdd p0[6], a, i, m p0[4], a, i, m p0[2], a, i, m m, p3[1] m, 12c scl, p1[7] p0[0], a, i, m p2[6], m p3[0], m xres m, 12c sda, p1[5] m, p1[3] m, 12c scl, p1[1] vss m, 12c sda, p1[0] m, p1[2] m, extclk, p1[4] m, p1[6] p2[4], m p2[2], m p2[0], m p3[2], m p0[5], a, i, m figure 6. cy7c60323-lfxc 32-pin device figure 7. CY7C60333-LFXC 32-pin device figure 8. cy7c60323-ltxc 32-pin device figure 9. cy7c60333-ltxc 32-pin device note 1. the qfn package has a center pad that must be connected to ground (vss). [+] feedback
cy7c603xx document number: 38-16018 rev. *g page 10 of 34 table 4. 32-pin part pinout (qfn [1] ) pin no. type name description digital analog 1 io i, m p0[1] analog column mux input, integrating input. 2 io m p2[7] 3 io m p2[5] 4 io m p2[3] 5 io m p2[1] 6 io m p3[3] in cy7c60323 part. 6 power smp switch mode pump (smp) connection to required external components in cy7c60333 part. 7 io m p3[1] in cy7c60323 part. 7 power vss ground connection in cy7c60333 part. 8 io m p1[7] i2c serial clock (scl). 9 io m p1[5] i2c serial data (sda). 10 io m p1[3] 11 io m p1[1] i2c serial clock (scl), issp-sclk. 12 power vss ground connection. 13 io m p1[0] i2c serial data (sda), issp-sdata. 14 io m p1[2] 15 io m p1[4] optional external clock input (extclk). 16 io m p1[6] 17 input xres active high external reset with internal pull down. 18 io m p3[0] 19 io m p3[2] 20 io m p2[0] 21 io m p2[2] 22 io m p2[4] 23 io m p2[6] 24 io i, m p0[0] analog column mux input. 25 io i, m p0[2] analog column mux input. 26 io i, m p0[4] analog column mux input. 27 io i, m p0[6] analog column mux input. 28 power vdd supply voltage. 29 io i, m p0[7] analog column mux input. 30 io i, m p0[5] analog column mux input. 31 io i, m p0[3] analog column mux input, integrating input. 32 power vss ground connection. legend a = analog, i = input, o = output, and m = analog mux input. [+] feedback
cy7c603xx document number: 38-16018 rev. *g page 11 of 34 register reference this section lists the registers of the encore iii lv device. for detailed register information, refer the psoc system-on-chip technical reference manual . register conventions the register conventions specific to this section are listed in ta b l e 5 . register mapping tables the encore iii lv device has a total register address space of 512 bytes. the register space is referred to as io space and is divided into two banks. the xoi bit in the flag register (cpu_f) determines which bank the user is currently in. when the xoi bit is set the user is in bank 1. note in the following register mapping tables, blank fields are reserved and must not be accessed. table 5. register conventions convention description r read register or bit(s) w write register or bit(s) l logical register or bit(s) c clearable register or bit(s) # access is bit specific table 6. register map 0 table: user space name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access prt0dr 00 rw 40 ase10cr0 80 rw c0 prt0ie 01 rw 41 81 c1 prt0gs 02 rw 42 82 c2 prt0dm2 03 rw 43 83 c3 prt1dr 04 rw 44 ase11cr0 84 rw c4 prt1ie 05 rw 45 85 c5 prt1gs 06 rw 46 86 c6 prt1dm2 07 rw 47 87 c7 prt2dr 08 rw 48 88 c8 prt2ie 09 rw 49 89 c9 prt2gs 0a rw 4a 8a ca prt2dm2 0b rw 4b 8b cb prt3dr 0c rw 4c 8c cc prt3ie 0d rw 4d 8d cd prt3gs 0e rw 4e 8e ce prt3dm2 0f rw 4f 8f cf 10 50 90 cur_pp d0 rw 11 51 91 stk_pp d1 rw 12 52 92 d2 13 53 93 idx_pp d3 rw 14 54 94 mvr_pp d4 rw 15 55 95 mvw_pp d5 rw 16 56 96 i2c_cfg d6 rw 17 57 97 i2c_scr d7 # 18 58 98 i2c_dr d8 rw 19 59 99 i2c_mscr d9 # 1a 5a 9a int_clr0 da rw 1b 5b 9b int_clr1 db rw 1c 5c 9c dc blank fields are reserved and must not be accessed. # access is bit specific. [+] feedback
cy7c603xx document number: 38-16018 rev. *g page 12 of 34 1d 5d 9d int_clr3 dd rw 1e 5e 9e int_msk3 de rw 1f 5f 9f df dbb00dr0 20 # amx_in 60 rw a0 int_msk0 e0 rw dbb00dr1 21 w amuxcfg 61 rw a1 int_msk1 e1 rw dbb00dr2 22 rw pwm_cr 62 rw a2 int_vc e2 rc dbb00cr0 23 # 63 a3 res_wdt e3 w dbb01dr0 24 # cmp_cr0 64 # a4 e4 dbb01dr1 25 w 65 a5 e5 dbb01dr2 26 rw cmp_cr1 66 rw a6 dec_cr0 e6 rw dbb01cr0 27 # 67 a7 dec_cr1 e7 rw dcb02dr0 28 # adc0_cr 68 # a8 e8 dcb02dr1 29 w adc1_cr 69 # a9 e9 dcb02dr2 2a rw 6a aa ea dcb02cr0 2b # 6b ab eb dcb03dr0 2c # tmp_dr0 6c rw ac ec dcb03dr1 2d w tmp_dr1 6d rw ad ed dcb03dr2 2e rw tmp_dr2 6e rw ae ee dcb03cr0 2f # tmp_dr3 6f rw af ef 30 70 rdi0ri b0 rw f0 31 71 rdi0syn b1 rw f1 32 ace00cr1 72 rw rdi0is b2 rw f2 33 ace00cr2 73 rw rdi0lt0 b3 rw f3 34 74 rdi0lt1 b4 rw f4 35 75 rdi0ro0 b5 rw f5 36 ace01cr1 76 rw rdi0ro1 b6 rw f6 37 ace01cr2 77 rw b7 cpu_f f7 rl 38 78 b8 f8 39 79 b9 f9 3a 7a ba fa 3b 7b bb fb 3c 7c bc fc 3d 7d bd dac_d fd rw 3e 7e be cpu_scr1 fe # 3f 7f bf cpu_scr0 ff # table 6. register map 0 table: user space (continued) name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access blank fields are reserved and must not be accessed. # access is bit specific. [+] feedback
cy7c603xx document number: 38-16018 rev. *g page 13 of 34 table 7. register map 1 table: configuration space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access prt0dm0 00 rw 40 ase10cr0 80 rw c0 prt0dm1 01 rw 41 81 c1 prt0ic0 02 rw 42 82 c2 prt0ic1 03 rw 43 83 c3 prt1dm0 04 rw 44 ase11cr0 84 rw c4 prt1dm1 05 rw 45 85 c5 prt1ic0 06 rw 46 86 c6 prt1ic1 07 rw 47 87 c7 prt2dm0 08 rw 48 88 c8 prt2dm1 09 rw 49 89 c9 prt2ic0 0a rw 4a 8a ca prt2ic1 0b rw 4b 8b cb prt3dm0 0c rw 4c 8c cc prt3dm1 0d rw 4d 8d cd prt3ic0 0e rw 4e 8e ce prt3ic1 0f rw 4f 8f cf 10 50 90 gdi_o_in d0 rw 11 51 91 gdi_e_in d1 rw 12 52 92 gdi_o_ou d2 rw 13 53 93 gdi_e_ou d3 rw 14 54 94 d4 15 55 95 d5 16 56 96 d6 17 57 97 d7 18 58 98 mux_cr0 d8 rw 19 59 99 mux_cr1 d9 rw 1a 5a 9a mux_cr2 da rw 1b 5b 9b mux_cr3 db rw 1c 5c 9c dc 1d 5d 9d osc_go_en dd rw 1e 5e 9e osc_cr4 de rw 1f 5f 9f osc_cr3 df rw dbb00fn 20 rw clk_cr0 60 rw a0 osc_cr0 e0 rw dbb00in 21 rw clk_cr1 61 rw a1 osc_cr1 e1 rw dbb00ou 22 rw abf_cr0 62 rw a2 osc_cr2 e2 rw 23 amd_cr0 63 rw a3 vlt_cr e3 rw dbb01fn 24 rw cmp_go_en 64 rw a4 vlt_cmp e4 r dbb01in 25 rw 65 a5 adc0_tr e5 rw dbb01ou 26 rw amd_cr1 66 rw a6 adc1_tr e6 rw 27 alt_cr0 67 rw a7 e7 dcb02fn 28 rw 68 a8 imo_tr e8 w dcb02in 29 rw 69 a9 ilo_tr e9 w dcb02ou 2a rw 6a aa bdg_tr ea rw 2b clk_cr3 6b rw ab eco_tr eb w blank fields are reserved and must not be accessed. # access is bit specific. [+] feedback
cy7c603xx document number: 38-16018 rev. *g page 14 of 34 dcb03fn 2c rw tmp_dr0 6c rw ac ec dcb03in 2d rw tmp_dr1 6d rw ad ed dcb03ou 2e rw tmp_dr2 6e rw ae ee 2f tmp_dr3 6f rw af ef 30 70 rdi0ri b0 rw f0 31 71 rdi0syn b1 rw f1 32 ace00cr1 72 rw rdi0is b2 rw f2 33 ace00cr2 73 rw rdi0lt0 b3 rw f3 34 74 rdi0lt1 b4 rw f4 35 75 rdi0ro0 b5 rw f5 36 ace01cr1 76 rw rdi0ro1 b6 rw f6 37 ace01cr2 77 rw b7 cpu_f f7 rl 38 78 b8 f8 39 79 b9 f9 3a 7a ba fls_pr1 fa rw 3b 7b bb fb 3c 7c bc fc 3d 7d bd dac_cr fd rw 3e 7e be cpu_scr1 fe # 3f 7f bf cpu_scr0 ff # table 7. register map 1 table: configuration space (continued) name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access blank fields are reserved and must not be accessed. # access is bit specific. [+] feedback
cy7c603xx document number: 38-16018 rev. *g page 15 of 34 electrical specifications this section presents the dc and ac electr ical specifications of the encore iii lv dev ice. for the most up to date electrical specifications, check the latest data sheet by visiting the web at http://www.cypress.com/go/usb . specifications are valid for 0c t a 70c and t j 85c as specified, except where noted. refer to table 20 on page 22 for the electrical spec ifications on the internal main oscillator (imo) using slimo mode. figure 10. voltage versus cpu frequency figure 11. imo frequency trim options the allowable cpu operating region for 12 mhz has been extended down to 2.7v from the original 3.0v design target. the customer 's application is responsible for monitoring voltage and throttling back cpu speed in accordance with figure 10 when voltage approaches 2.7v. refer to ta b l e 1 8 for lvd specifications. note that the device does not support a preset trip at 2.7v. to detect vdd drop at 2.7v, an external circuit or device such as the wirele ssusb lp - cyrf6936 must be employed; or if the design permits, t he nearest lvd trip value at 2.9v can be used. ta b l e 8 lists the units of measure t hat are used in this section. 3.60 v 3.00 v 93 khz 12 mhz cpu frequency vdd voltage 2.40 v 3 mhz valid operating region 2.70 v 3.00 v 93 khz 12 mhz 24 mhz imo frequency vdd voltage 3.60 v 6 mhz 2.40 v slimo mode=1 slimo mode=1 slimo mode=1 slimo mode=0 table 8. units of measure symbol unit of measure symbol unit of measure c degree celsius w microwatts db decibels ma milliampere ff femtofarad ms millisecond hz hertz mv millivolts kb 1024 bytes na nanoampere kbit 1024 bits ns nanosecond khz kilohertz nv nanovolts k kilohm ohm mhz megahertz pa picoampere m megaohm pf picofarad a microampere pp peak-to-peak f microfarad ppm parts per million h microhenry ps picosecond s microsecond sps samples per second v microvolts s sigma: one standard deviation vrms microvolts root-mean-square v volts [+] feedback
cy7c603xx document number: 38-16018 rev. *g page 16 of 34 absolute maximum ratings operating temperature dc electrical characteristics dc chip-level specifications ta b l e 11 lists guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 3.0v to 3.6v and 0 c< t a < 70 c, or 2.4v to 3.0v and 0 c < t a < 70 c, respectively. typical parameters apply to 3.3v, or 2.7v at 25 c and are for design guidance only. table 9. absolute maximum ratings parameter description min typ max unit notes t stg storage temperature ?40 ? +90 c higher storage temperatures reduce data retention time. t a ambient temperature with power applied 0 ? +70 c vdd supply voltage on vdd relative to vss ?0.5 ? 5 v v io dc input voltage vss ? 0.5 ? vdd + 0.5 v v ioz dc voltage applied to tri-state vss ? 0.5 ? vdd + 0.5 v i mio maximum current into any port pin ?25 ? +25 ma esd electro static discharge voltage 2000 ? ? v human body model esd. lu latch up current ? ? 200 ma table 10. operating temperature parameter description min typ max unit notes t a ambient temperature 0 ? +70 c t j junction temperature 0 ? +85 c the temperature rise from ambient to junction is package specific. see table 33 on page 31. the user must limit the power consumption to comply with this requirement. table 11. dc chip-level specifications parameter description min typ max unit notes vdd supply voltage 2.40 ? 3.6 v see table 18 on page 20. i dd3 supply current, imo = 6 mhz using slimo mode. ? 1.2 2 ma conditions are vdd = 3.3v, t a = 25c, cpu = 3 mhz, clock doubler disabled. vc1 = 375 khz, vc2 = 23.4 khz, vc3 = 0.091 khz. i dd27 supply current, imo = 6 mhz using slimo mode. ? 1.1 1.5 ma conditions are vdd = 2.55v, t a = 25c, cpu = 3 mhz, clock doubler disabled. vc1 = 375 khz, vc2 = 23.4 khz, vc3 = 0.091 khz. i sb27 sleep (mode) current with por, lvd, sleep timer, wdt, and internal slow oscillator active. mid temperature range. ? 2.6 4. a vdd = 2.55v, 0c < t a < 40c. i sb sleep (mode) current with por, lvd, sleep timer, wdt, and internal slow oscillator active. ? 2.8 5 a vdd = 3.3v, 0c < t a < 70c. v ref reference voltage (bandgap) 1.28 1.30 1.32 v trimmed for appropriate vdd. vdd = 3.0v to 3.6v. v ref27 reference voltage (bandgap) 1.16 1.30 1.33 v trimmed for appropriate vdd. vdd = 2.4v to 3.0v. agnd analog ground v ref ? 0.003 v ref v ref + 0.003 v [+] feedback
cy7c603xx document number: 38-16018 rev. *g page 17 of 34 dc general purpose io specifications the following tables list guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 3.0v to 3.6v an d 0 c < t a < 70 c, or 2.4v to 3.0v and 0 c < t a < 70 c, respectively. typical parameters apply to 3.3v, and 2.7v at 25 c and are for design guidance only. table 12. 3.3v dc gpio specifications parameter description min typ max unit notes r pu pull up resistor 4 5.6 8 k r pd pull down resistor 4 5.6 8 k v oh high output level vdd ? 1.0 ?? vi oh = 3 ma, v dd > 3.0v v ol low output level ? ? 0.75 v i ol = 10 ma, v dd > 3.0v i oh high level source current 3 ? ? ma i ol low level sink current 10 ? ? ma v il input low level ? ? 0.8 v vdd = 3.0 to 3.6. v ih input high level 2.1 ? v vdd = 3.0 to 3.6. v h input hysteresis ? 60 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 a. c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent. te m p = 2 5 c . c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent. te m p = 2 5 c . table 13. 2.7v dc gpio specifications parameter description min typ max unit notes r pu pull up resistor 4 5.6 8 k r pd pull down resistor 4 5.6 8 k v oh high output level vdd ? 0.4 ?? vi oh = 2.5 ma (6.25 typ), v dd = 2.4 to 3.0v (16 ma maximum, 50 ma typ combined i oh budget). v ol low output level ? ? 0.75 v i ol = 10 ma, v dd = 2.4 to 3.0v (90 ma maximum combined i ol budget). i oh high level source current 2.5 ? ? ma i ol low level sink current 10 ? ? ma v il input low level ? ? 0.75 v vdd = 2.4 to 3.0. v ih input high level 2.0 ? ? v vdd = 2.4 to 3.0. v h input hysteresis ? 90 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 a. c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent. te m p = 2 5 c . c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent. te m p = 2 5 c . [+] feedback
cy7c603xx document number: 38-16018 rev. *g page 18 of 34 dc operational amplifier specifications the following tables list guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 3.0v to 3.6v an d 0 c < t a < 70 c, or 2.4v to 3.0v and 0 c < t a < 70 c, respectively. typical parameters apply to 3.3v, or 2.7v at 25 c and are for design guidance only. table 14. 3.3v dc operational amplifier specifications parameter description min typ max unit notes v osoa input offset voltage (absolute value) ? 2.5 15 mv tcv osoa average input offset voltage drift ? 10 ? v/c i eboa [2] input leakage current (port 0 analog pins) ? 200 ? pa gross tested to 1 a. c inoa input capacitance (port 0 analog pins ) ? 4.5 9.5 pf package and pin dependent. te m p = 2 5 c . v cmoa common mode voltage range 0 ? vdd ? 1 v g oloa open loop gain ? 80 ? db i soa amplifier supply current ? 10 30 a note 2. atypical behavior: i eboa of port 0 pin 0 is below 1 na at 25c; 50 na over temper ature. use port 0 pins 1?7 for the lowest leakage of 200 na. table 15. 2.7v dc operational amplifier specifications parameter description min typ max unit notes v osoa input offset voltage (absolute value) ? 2.5 15 mv tcv osoa average input offset voltage drift ? 10 ? v/c i eboa [2] input leakage current (port 0 analog pins) ? 200 ? pa gross tested to 1 a. c inoa input capacitance (port 0 analog pins ) ? 4.5 9.5 pf package and pin dependent. te m p = 2 5 c . v cmoa common mode voltage range 0 ? vdd ? 1 v g oloa open loop gain ? 80 ? db i soa amplifier supply current ? 10 30 a [+] feedback
cy7c603xx document number: 38-16018 rev. *g page 19 of 34 dc switch mode pump specifications ta b l e 1 6 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0v to 3.6v and 0 c< t a < 70 c, or 2.4v to 3.0v and 0 c < t a < 70 c, respectively. typical paramete rs apply to 3.3v, or 2.7v at 25 c and are for design guidance only. table 16. dc switch mode pump (smp) specifications parameter description min typ max unit notes v pump3v 3.3v output voltage from pump 3.00 3.25 3.60 v configuration of footnote. [3] average, neglecting ripple. smp trip voltage is set to 3.25v. v pump2v 2.6v output voltage from pump 2.45 2.55 2.80 v configuration of footnote. [3] average, neglecting ripple. smp trip voltage is set to 2.55v. i pump available output current v bat = 1.5v, v pump = 3.25v v bat = 1.3v, v pump = 2.55v 8 8 ? ? ? ? ma ma configuration of footnote. [3] smp trip voltage is set to 3.25v. smp trip voltage is set to 2.55v. v bat3v input voltage range from battery 1.0 ? 3.3 v configuration of footnote. [3] smp trip voltage is set to 3.25v. v bat2v input voltage range from battery 1.0 ? 2.8 v configuration of footnote. [3] smp trip voltage is set to 2.55v. v batstart minimum input voltage from battery to start pump 1.2 ? ? v configuration of footnote. [3] 0c < t a < 100. 1.25v at t a = ?40c. v pump_li ne line regulation (over vi range) ? 5 ? %v o configuration of footnote. [3] v o is the ?vdd value for pump trip? specified by the vm[2:0] setting in the dc por and lvd specification, table 18 on page 20. v pump_lo ad load regulation ? 5 ? %v o configuration of footnote. [3] v o is the ?vdd value for pump trip? specified by the vm[2:0] setting in the dc por and lvd specification, table 18 on page 20. v pump_ri pple output voltage ripple (depends on cap/load) ? 100 ? mvpp configuration of footnote. [3] load is 5 ma. e 3 efficiency 35 50 ? % configuration of footnote. [3] load is 5 ma. smp trip voltage is set to 3.25v. e 2 efficiency 35 80 ? % for i load = 1 ma, v pump = 2.55v, v bat = 1.3v, 10 h inductor, 1 f capacitor, and schottky diode. f pump switching frequency ? 1.3 ? mhz dc pump switching duty cycle ? 50 ? % note 3. l 1 = 2 h inductor, c 1 = 10 f capacitor, d 1 = schottky diode. see figure 12 on page 20. [+] feedback
cy7c603xx document number: 38-16018 rev. *g page 20 of 34 figure 12. basic switch mode pump circuit dc analog mux bus specifications ta b l e 1 7 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0v to 3.6v and 0 c < t a < 70 c, or 2.4v to 3.0v and 0 c < t a < 70 c, respectively. typical paramete rs apply to 3.3v, or 2.7v at 25 c and are for design guidance only. dc por and lvd specifications ta b l e 1 8 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0v to 3.6v and 0 c < t a < 70 c, or 2.4v to 3.0v and 00 c < t a < 70 c, respectively. typical parameters apply to 3.3v, or 2.7v at 25 c and are for design guidance only. battery c 1 d 1 + encore iii lv vdd vss smp v bat l 1 v pump table 17. dc analog mux bus specifications parameter description min typ max unit notes r sw switch resistance to common analog bus ? ? 400 800 vdd > 2.7v 2.4v < vdd < 2.7v r vdd resistance of initialization switch to vdd ? ? 800 table 18. dc por and lvd specifications parameter description min typ max unit notes v ppor0 v ppor1 vdd value for ppor trip porlev[1:0] = 00b porlev[1:0] = 01b ? 2.36 2.82 2.40 2.95 v v vdd must be greater than or equal to 2.5v during startup, reset from the xres pin, or reset from watchdog. vdd value for lvd trip v lvd0 vm[2:0] = 000b 2.40 2.45 2.51 [4] v v lvd1 vm[2:0] = 001b 2.85 2.92 2.99 [5] v v lvd2 vm[2:0] = 010b 2.95 3.02 3.09 v v lvd37 vm[2:0] = 011b 3.06 3.13 3.20 v vdd value for pump trip v pump0 vm[2:0] = 000b 2.45 2.55 2.62 [6] v v pump1 vm[2:0] = 001b 2.96 3.02 3.09 v v pump2 vm[2:0] = 010b 3.03 3.10 3.16 v v pump3 vm[2:0] = 011b 3.18 3.25 3.32 [7] v notes 4. always greater than 50 mv above vppor (porlev = 00) for falling supply. 5. always greater than 50 mv above vppor (porlev = 01) for falling supply. 6. always greater than 50 mv above vlvd0. 7. always greater than 50 mv above vlvd3. [+] feedback
cy7c603xx document number: 38-16018 rev. *g page 21 of 34 dc programming specifications ta b l e 1 9 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0v to 3.6v and 0 c < t a < 70 c, or 2.4v to 3.0v and 0 c < t a < 70 c, respectively. typical paramete rs apply to 3.3v, or 2.7v at 25 c and are for design guidance only. table 19. dc programming specifications parameter description min typ max unit notes vdd iwrite supply voltage for flash write operations 2.70 ? ? v i ddp supply current during programming or verify ? 5 25 ma v ilp input low voltage during programming or verify ? ? 0.8 v v ihp input high voltage during programming or verify 2.1 ? ? v i ilp input current when applying vilp to p1[0] or p1[1] during programming or verify ? ? 0.2 ma driving internal pull down resistor. i ihp input current when applying vihp to p1[0] or p1[1] during programming or verify ? ? 1.5 ma driving internal pull down resistor. v olv output low voltage during programming or verify ? ? vss + 0.75 v v ohv output high voltage during programming or verify vdd ? 1.0 ? vdd v flash enpb flash endurance (per block) 50,000 [8] ? ? ? erase/write cycles per block. flash ent flash endurance (total) [9] 1,800,000 ? ? ? erase/write cycles. flash dr flash data retention 10 ? ? years notes 8. the 50,000 cycle flash endurance per block will only be guaranteed if the flash is operating within one voltage range. voltag e ranges are 2.4v to 3.0v and 3.0v to 3.6v. 9. a maximum of 36 x 50,000 block endurance cycles is allowed. th is may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 ma ximum cycles each (to limit the total number of cycles to 36x5 0,000 and that no single block ever sees more than 50,000 cycles). [+] feedback
cy7c603xx document number: 38-16018 rev. *g page 22 of 34 ac electrical characteristics ac chip-level specifications the following tables list guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 3.0v to 3.6v an d 0 c < t a < 70 c, or 2.4v to 3.0v and 0 c < t a < 70 c, respectively. typical parameters apply to 3.3v, or 2.7v at 25 c and are for design guidance only. table 20. 3.3v ac chip-level specifications parameter description min typ max unit notes f imo24 internal main oscillator frequency for 24 mhz 23.4 24 24.6 [10, 11] mhz trimmed for 3.3v operation using factory trim values. see figure 11 on page 15. slimo mode = 0. f imo6 internal main oscillator frequency for 6 mhz 5.5 6 6.5 [10, 11] mhz trimmed for 3.3v operation using factory trim values. see figure 11 on page 15. slimo mode = 1. f cpu2 cpu frequency (3.3v nominal) 0.93 12 12.3 [10, 11] mhz f blk33 digital block frequency (3.3v nominal) 0 24 24.6 [10, 12] mhz f 32k1 internal low speed oscillator frequency 15 32 64 khz f 32k_u internal low speed oscillator untrimmed frequency 5 ? ? khz dc ilo internal low speed oscillator duty cycle 20 50 80 % jitter32k 32 khz rms period jitter ? 100 200 ns jitter32k 32 khz peak-to-peak period jitter ? 1400 ? t xrst external reset pulse width 10 ? ? s dc24m 24 mhz duty cycle 40 50 60 % step24m 24 mhz trim step size ? 50 ? khz fout48m 48 mhz output frequency 46.8 48.0 49.2 [11] mhz trimmed. using factory trim values. jitter24m1 24 mhz peak-to-peak period jitter (imo) ? 600 ps f max maximum frequency of signal on row input or row output. ? ? 12.3 mhz sr power_ up power supply slew rate ? ? 250 v/ms t powerup time from end of por to cpu executing code ? 16 100 ms [+] feedback
cy7c603xx document number: 38-16018 rev. *g page 23 of 34 figure 13. 24 mhz period jitter (imo) timing diagram figure 14. 32 khz period jitter (ilo) timing diagram notes 10. accuracy derived from internal main oscillator with appropriate trim for vdd range. 11. 3.0v < vdd < 3.6v. 12. see the individual user module data sheets for information on maximum frequencies for user modules. 13. 2.4v < vdd < 3.0v. table 21. 2.7v ac chip-level specifications parameter description min typ max unit notes f imo12 internal main oscillator frequency for 12 mhz 11.5 12 0 12.7 [10, 13] mhz trimmed for 2.7v operation using factory trim values. see figure 11 on page 15. slimo mode = 1. f imo6 internal main oscillator frequency for 6 mhz 5.5 6 6.5 [10, 13] mhz trimmed for 2.7v operation using factory trim values. see figure 11 on page 15. slimo mode = 1. f cpu1 cpu frequency (2.7v nominal) 0.093 3 3.15 [10, 13] mhz 24 mhz only for slimo mode = 0. f blk27 digital block frequency (2.7v nominal) 0 12 12.5 [10, 13] mhz refer to the ac digital block specifications. f 32k1 internal low speed oscillator frequency 8 32 96 khz f 32k_u internal low speed oscillator untrimmed frequency 5 ? ? khz dc ilo internal low speed oscillator duty cycle 20 50 80 % jitter32k 32 khz rms period jitter ? 150 200 ns jitter32k 32 khz peak-to-peak period jitter ? 1400 ? t xrst external reset pulse width 10 ? ? s f max maximum frequency of signal on row input or row output. ? ? 12.3 mhz sr power_ up power supply slew rate ? ? 250 v/ms t powerup time from end of por to cpu executing code ? 16 100 ms jitter24m1 f 24m jitter32k f 32k1 [+] feedback
cy7c603xx document number: 38-16018 rev. *g page 24 of 34 ac general purpose io specifications the following tables list guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 3.0v to 3.6v an d 0 c < t a < 70 c, or 2.4v to 3.0v and 0 c < t a < 70 c, respectively. typical parameters apply to 3.3v, or 2.7v at 25 c and are for design guidance only. figure 15. gpio timing diagram ac operational amplifier specifications ta b l e 2 4 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0v to 3.6v and 0 c < t a < 70 c, or 2.4v to 3.0v and 0 c < t a < 70 c, respectively. typical paramete rs apply to 3.3v, or 2.7v at 25 c and are for design guidance only. table 22. 3.3v ac gpio specifications parameter description min typ max unit notes f gpio gpio operating frequency 0 ? 12 mhz normal strong mode trises rise time, slow strong mode, cload = 50 pf 7 27 ? ns vdd = 3 to 3.6v, 10%?90% tfalls fall time, slow strong mode, cload = 50 pf 7 22 ? ns vdd = 3 to 3.6v, 10%?90% table 23. 2.7v ac gpio specifications parameter description min typ max unit notes f gpio gpio operating frequency 0 ? 3 mhz normal strong mode trisef rise time, normal strong mode, cload = 50 pf 6 ? 50 ns vdd = 2.4 to 3.0v, 10%?90% tfallf fall time, normal strong mode, cload = 50 pf 6 ? 50 ns vdd = 2.4 to 3.0v, 10%?90% trises rise time, slow strong mode, cload = 50 pf 18 40 120 ns vdd = 2.4 to 3.0v, 10%?90% tfalls fall time, slow strong mode, cload = 50 pf 18 40 120 ns vdd = 2.4 to 3.0v, 10%?90% tfallf tfalls trisef tr is es 90% 10% gpio pin output voltage table 24. ac operational amplifier specifications parameter description min typ max unit notes t comp comparator mode response time, 50 mv overdrive 100 200 ns ns vdd > 3.0v. 2.4v < vcc < 3.0v. [+] feedback
cy7c603xx document number: 38-16018 rev. *g page 25 of 34 ac analog mux bus specifications ta b l e 2 5 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0v to 3.6v and 0 c < t a < 70 c, or 2.4v to 3.0v and 0 c < t a < 70 c, respectively. typical paramete rs apply to 3.3v, or 2.7v at 25 c and are for design guidance only. ac digital block specifications the following tables list guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 3.0v to 3.6v an d 0 c < t a < 70 c, or 2.4v to 3.0v and 0 c < t a < 70 c, respectively. typical parameters apply to 3.3v, or 2.7v at 25 c and are for design guidance only. table 25. ac analog mux bus specifications parameter description min typ max unit notes f sw switch rate ? ? 3.17 mhz table 26. 3.3v ac digital block specifications function description min typ max unit notes all functions maximum block clocking frequency (< 3.6v) 24.6 mhz 3.0v < vdd < 3.6v. timer/ counter/ pwm enable pulse width 50 [14] ? ? ns maximum frequency ? ? 24.6 mhz dead band kill pulse width: asynchronous restart mode 20 ? ? ns synchronous restart mode 50 ? ? ns disable mode 50 ? ? ns maximum frequency ? ? 49.2 mhz 4.75v < vdd < 5.25v. spim maximum input clock frequency ? ? 8.2 mhz maximum data rate at 4.1 mhz due to 2 x over clocking. spis maximum input clock frequency ? ? 4.1 mhz width of ss_ negated between transmis- sions 50 ? ? ns transmitter maximum input clock frequency ? ? 24.6 mhz maximum data rate at 3.08 mhz due to 8 x over clocking. receiver maximum input clock frequency ? ? 24.6 mhz maximum data rate at 3.08 mhz due to 8 x over clocking. note 14. 50 ns minimum input pulse width is based on the input synchronizers running at 12 mhz (84 ns nominal period). [+] feedback
cy7c603xx document number: 38-16018 rev. *g page 26 of 34 ac external clock specifications the following tables list guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 3.0v to 3.6v an d 0 c < t a < 70 c, respectively. typical parameters apply to 3.3v, or 2.7v at 25 c and are for design guidance only. table 27. 2.7v ac digital block specifications function description min typ max unit notes all functions maximum block clocking frequency 12.7 mhz 2.4v < vdd < 3.0v. timer/ counter/ pwm enable pulse width 100 ? ? ns maximum frequency ? ? 12.7 mhz dead band kill pulse width: asynchronous restart mode 20 ? ? ns synchronous restart mode 100 ? ? ns disable mode 100 ? ? ns maximum frequency ? ? 12.7 mhz spim maximum input clock frequency ? ? 6.35 mhz maximum data rate at 3.17 mhz due to 2 x over clocking. spis maximum input clock frequency ? ? 4.1 mhz width of ss_ negated between transmis- sions 100 ? ? ns transmitter maximum input clock frequency ? ? 12.7 mhz maximum data rate at 1.59 mhz due to 8 x over clocking. receiver maximum input clock frequency ? ? 12.7 mhz maximum data rate at 1.59 mhz due to 8 x over clocking. table 28. 3.3v ac external clock specifications parameter description min typ max unit notes f oscext frequency with cpu clock divide by 1 0.093 ? 12.3 mhz maximum cpu frequency is 12 mhz at 3.3v. with the cpu clock divider set to 1, the exte rnal clock must adhere to the maximum frequency and duty cycle requirements. f oscext frequency with cpu clock divide by 2 or greater 0.186 ? 24.6 mhz if the frequency of the external clock is greater than 12 mhz, the cpu clock divider must be set to 2 or greater. in this case, the cpu clock divider ensures that the fifty percent duty cycle requirement is met. ? high period with cpu clock divide by 1 41.7 ? 5300 ns ? low period with cpu clock divide by 1 41.7 ? ?ns ? power up imo to switch 150 ? ? s [+] feedback
cy7c603xx document number: 38-16018 rev. *g page 27 of 34 ac programming specifications ta b l e 3 0 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0v to 3.6v and 0 c < t a < 70 c, respectively. typical parameters apply to 3.3v, or 2.7v at 25 c and are for design guidance only. table 29. 2.7v ac external clock specifications parameter description min typ max unit notes f oscext frequency with cpu clock divide by 1 0.093 ?3.08 0 mhz maximum cpu frequency is 3 mhz at 2.7v. with the cpu clock divider set to 1, the exte rnal clock must adhere to the maximum frequency and duty cycle requirements. f oscext frequency with cpu clock divide by 2 or greater 0.186 ? 6.35 mhz if the frequency of the external clock is greater than 3 mhz, the cpu clock divider must be set to 2 or greater. in this case, the cpu clock divider ensures that the fifty percent duty cycle requirement is met. ? high period with cpu clock divide by 1 160 ? 5300 ns ? low period with cpu clock divide by 1 160 ? ?ns ? power up imo to switch 150 ? ? s table 30. ac programming specifications parameter description min typ max unit notes t rsclk rise time of sclk 1 ? 20 ns t fsclk fall time of sclk 1 ? 20 ns t ssclk data set up time to falling edge of sclk 40 ? ? ns t hsclk data hold time from falling edge of sclk 40 ? ? ns f sclk frequency of sclk 0 ? 8 mhz t eraseb flash erase time (block) ? 10 ? ms t write flash block write time ? 40 ? ms t dsclk3 data out delay from falling edge of sclk ? ? 50 ns 3.0 vdd 3.6 t dsclk2 data out delay from falling edge of sclk ? ? 70 ns 2.4 vdd 3.0 t eraseall flash erase time (bulk) ? 20 ? ms erase all blocks and protection fields at once. t program _hot flash block erase + flash block write time ? ? 100 ms 0c t j 100c t program _cold flash block erase + flash block write time ? ? 200 ms -40c t j 0c [+] feedback
cy7c603xx document number: 38-16018 rev. *g page 28 of 34 ac i 2 c specifications the following tables list guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 3.0v to 3.6v an d 0 c < t a < 70 c, or 2.4v to 3.0v and 0 c < t a < 70 c, respectively. typical parameters apply to 3.3v, or 2.7v at 25 c and are for design guidance only. figure 16. definition of timing for fast-/standard-mode on the i 2 c bus table 31. ac characteristics of the i 2 c sda and scl pins for vdd > 3.0v parameter description standard-mode fast-mode unit min max min max f scli2c scl clock frequency 0 100 0 400 khz t hdstai2c hold time (repeated) start conditio n. after this period, the first clock pulse is generated. 4.0 ?0.6 ? s t lowi2c low period of the scl clock 4.7 ?1.3 ? s t highi2c high period of the scl clock 4.0 ?0.6 ? s t sustai2c set up time for a repeated start condition 4.7 ?0.6 ? s t hddati2c data hold time 0 ?0 ? s t sudati2c data setup time 250 ?100 [15] ?ns t sustoi2c set up time for stop condition 4.0 ?0.6 ? s t bufi2c bus free time between a stop and start condition 4.7 ?1.3 ? s t spi2c pulse width of spikes are suppressed by the input filter. ? ? 0 50 ns note 15. a fast-mode i2c-bus device can be used in a standard-mode i2c-bus system, but the requirement t su;dat > 250 ns must then be met. this is automatically the case if the device does not stretch the low peri od of the scl signal. if such device does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i2 c-bus specification) before the scl line is released. table 32. 2.7v ac characteristics of the i 2 c sda and scl pins (fast-mode not supported) parameter description standard-mode fast-mode unit min max min max f scli2c scl clock frequency 0 100 ? ? khz t hdstai2c hold time (repeated) start conditio n. after this period, the first clock pulse is generated. 4.0 ? ? ? s t lowi2c low period of the scl clock 4.7 ? ? ? s t highi2c high period of the scl clock 4.0 ? ? ? s t sustai2c setup time for a repeated start condition 4.7 ? ? ? s t hddati2c data hold time 0 ? ? ? s t sudati2c data setup time 250 ? ? ?ns t sustoi2c setup time for stop condition 4.0 ? ? ? s t bufi2c bus free time between a stop and start condition 4.7 ?? ? s t spi2c pulse width of spikes are suppressed by the input filter. ? ?? ?ns sda scl s sr s p t bufi2c t spi2c t hdstai2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c [+] feedback
cy7c603xx document number: 38-16018 rev. *g page 29 of 34 packaging information this section illustrates the packaging specifications for the cy7c603xx device, along with the thermal impedances for each pack age. important note emulation tools may require a larger ar ea on the target pcb than the chip?s footprint. for a detailed description of the emulation tools? dimensions, refer to the document titled psoc emulator pod dimensions at http://www.cypress.com/support . packaging dimensions figure 17. 28-pin (210-mil) ssop 51-85079 *d [+] feedback
cy7c603xx document number: 38-16018 rev. *g page 30 of 34 figure 18. 32-pin qfn (5 x 5 mm) (punch) figure 19. 32-pin qfn (5 x 5 mm) (sawn) 51-85188 *d 001-30999 *c [+] feedback
cy7c603xx document number: 38-16018 rev. *g page 31 of 34 thermal impedances solder reflow peak temperature following is the minimum solder reflow peak temperature to achieve good solderability. table 33. thermal impedances per package package typical ja [16] typical jc 28 ssop 96 c/w 39 c/w 32 qfn 22 c/w 12 c/w table 34. solder reflow peak temperature package minimum peak temperature [17] maximum peak temperature 28 ssop 240c 260c 32 qfn 240c 260c notes 16. t j = t a + power x ja 17. higher temperatures may be required based on the solder melti ng point. typical temperatures for solder are 2205c with sn-p b or 2455c with sn-ag-cu paste. refer to the solder manufacturer specifications. package handling some ic packages require baking before they are soldered onto a pcb to remove moisture that may have been absorbed after leavin g the factory. a label on the packaging has details about actual bak e temperature and the minimum bake time to remove this moistu re. the maximum bake time is the aggregate time that the parts are exposed to the bake temperature. exceeding this exposure time ma y degrade device reliability. parameter description min typ max unit t baketemp bake temperature 125 see package label c t baketime bake time see package label 72 hours [+] feedback
cy7c603xx document number: 38-16018 rev. *g page 32 of 34 ordering information the following table lists the cy7c603xx device?s key package features and ordering codes. table 35. cy7c603xx device key features and ordering information package type ordering part number flash size ram size smp i/o 28-ssop cy7c60323-pvxc 8k 512 no 24 28-ssop tape and reel cy7c60323-pvxct 8k 512 no 24 32-qfn cy7c60323-lfxc 8k 512 no 28 32-qfn tape and reel cy7c60323-lfxct 8k 512 no 28 32-qfn sawn cy7c60323-ltxc 8k 512 no 28 32-qfn sawn tape and reel cy7c60323-ltxct 8k 512 no 28 32-qfn CY7C60333-LFXC 8k 512 yes 26 32-qfn tape and reel CY7C60333-LFXCt 8k 512 yes 26 32-qfn sawn cy7c60333-ltxc 8k 512 yes 26 32-qfn sawn tape and reel cy7c60333-ltxct 8k 512 yes 26 [+] feedback
cy7c603xx document number: 38-16018 rev. *g page 33 of 34 document history page description title: cy7c603xx, encore? iii low voltage document number: 38-16018 rev. ecn no. orig. of change submission date description of change ** 339394 bon see ecn new advance data sheet. *a 399556 bha see ecn changed from advance information to preliminary. changed data sheet format. removed cy7c604xx. *b 461240 tyj see ecn modified figure 10 to include 2.7v vdd at 12 mhz operation. *c 470485 tyj see ecn corrected part numbers in secti on 4 to match with part numbers in ordering infor- mation. from cy7c60323-28pvxc, cy7c60323-56lfxc and cy7c60333-56lfxc to cy7c60323-pvxc, cy7c60323-lfxc and CY7C60333-LFXC respectively. changed from preliminary to final data sheet. *d 513713 kkvtmp see ecn change title from wireless encore ii to encore iii low voltage. applied new template formatting. *e 2197567 uvs/aesa see ecn a dded 32-pin sawn qfn pin diagram , package diagra m, and ordering information. *f 2620679 cmcc/pyr s 12/12/2008 added packaging handling information. deleted note regarding link to amkor.com for mlf package dimensions. *g 2852393 xut 01/15/2010 added table of contents . updated dc gpio, ac chip-level, and ac programming specifications as follows: replaced tramp (time) with srpowe r_up (slew rate) specification. added ioh, iol, dcilo, f32k_u, tpowerup, teraseall, tprogram_hot, and tprogram_cold specifications. updated copyright and sales, solutions, and legal information urls. updated 28-pin ssop and 32-pin qfn (punch and sawn) package diagrams. [+] feedback
document number: 38-16018 rev. *g revised january 15, 2010 page 34 of 34 playstation is a registered trademark of sony. microsoft and windows are registered trademarks of microsoft corporation. psoc designer? and encore? are trademarks and psoc? is a registered trademark of cypress semiconductor corporation. purchase of i 2 c components from cypress or one of its sublicensed a ssociated companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. as from october 1st, 2006 philips semiconductors has a new trade name - nxp sem iconductors. all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c603xx ? cypress semiconductor corporation, 2005-2008, 2010. the information contained herein is subject to change without notice. cyp ress semiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent o r other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malf unction or failure may reasonably be expected to result in s ignificant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufact urer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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